Current advances in through-silicon via (TSV) technology allow for the production of a thinner, lighter, and smaller interconnected circuit for various electronic devices. Typically, TSVs are manufactured by dry etching a silicon dioxide-based dielectric material to form holes (i.e., vias) and trenches for vertical and horizontal interconnects prior to deposition of a metal, e.g., copper, onto the surface. Because copper has the property of being a fast diffuser and can move quickly through the underlying dielectric layer to poison the device, a diffusion layer is typically applied to the substrate before deposition of the copper. Chemical-mechanical polishing (CMP) is employed to reduce the thickness of the copper over-layer, as well as the thickness of the diffusion barrier layer, until a planar surface that exposes elevated portions of the dielectric surface is obtained. The vias and trenches remain filled with electrically conductive copper forming the circuit interconnects.
In order to precisely polish electronic component surfaces, it has become necessary to develop CMP compositions that are compatible with a combination of surfaces being polished. However, due to the significant difference in chemical reactivity of metal and oxide-based dielectric materials, conventional CMP compositions result in widely differing removal rates of substrates containing both metal and oxide-based dielectric materials, which can result in the over-polishing of one layer and overall inefficiency.
Thus, there remains a need in the art for improved CMP compositions and CMP methods for substrates comprising both metal and oxide-based dielectric layers. Particularly, there exists a need for CMP compositions with tunable selectivities, allowing the end-user to easily optimize polishing performance for specific substrates. In addition, a need exists for CMP compositions and methods capable of being tuned by the end-user to non-selectively remove a metal layer and a dielectric layer with nearly equal polishing rates during a single CMP step.